1. Field of the Invention
The present invention relates to an interconnect used in a display device represented by a liquid crystal display device, a semiconductor device represented by an ULSI, or the like. And the present invention relates to an interconnect forming technique, a thin film transistor comprising interconnect structures, and a display device comprising interconnects or thin film transistors.
2. Description of the Related Art
In recent years, as a material for interconnects used in the field of semiconductors represented by LSIs and ULSIs, efforts have been made to examine copper (Cu), which offers a lower interconnect resistance than conventional interconnects composed of aluminum (Al) and which has a higher tolerance to electro-migration, stress-migration, or the like. These efforts have been propelled by the development of finer-grained structures resulting from an increase in the degree of integration, an increase in operating speed, and the like.
Further, also in the field of display devices represented by liquid crystal display devices and the like, it has been desirable to increase a display area and thus an interconnect length and to integrate peripheral circuit portions into a monolithic integrated circuit by incorporating various additional functions such as a driver circuit and an intra-pixel memory. Thus, there has been a demand for interconnects offering a reduced resistance as in the case with the field of semiconductors.
Copper is expected to be an interconnect material of the next generation because it offers a lower resistance and a higher tolerance to migration than Al, a conventional interconnect material.
However, with a combination of masking based on photo-lithography, reactive ion etching, and the like, which combination has hitherto been used to form fine interconnects, it is difficult to form fine interconnects using Cu. This is because a halide of copper has a low evaporation pressure, i.e. it is difficult to evaporate. That is, if copper is used to form a fine interconnect, an etching process must be executed at a temperature of 200 to 300° C. in order to volatilize and remove the halide formed by the etching. It has thus been difficult to form a fine copper interconnect on the basis of etching.
A forming method for a fine interconnect using copper is what is called a “damascene process” disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2001-189295 and Jpn. Pat. Appln. KOKAI Publication No. 11-135504. With this method, first, a trench with a desired interconnect pattern shape is formed in an insulator film on a substrate. A thin copper film is formed all over the insulator film and inside the interconnect trench so as to fill up the interconnect trench, using various methods including PVD (Physical Vapor Deposition) such as a sputtering process, a plating process, and CVD (Chemical Vapor Deposition) using an organic metal material. Subsequently, a polishing process such as CMP (Chemical Mechanical Polishing), etch-back, or the like is used to remove the thin copper film from the upper end surface of the filled-up trench. Thus, a filled-up copper interconnect pattern is formed with the thin copper film remaining only inside the trench.
Description will be given of a forming method for an interconnect using the above described damascene process. FIGS. 12A to 12E are sectional views showing an example of the steps of a forming method for an interconnect using the conventional damascene process.
First, an insulator film 132 is formed on a substrate 131 composed of glass or the like. A polishing stop film 133 is then formed on the insulator film 132. A photo resist film (photosensitive resin film) 134 is then formed on the polishing stop film 133. Subsequently, a PEP (Photo Engraving Process, i.e. what is called “photo-lithography”) is utilized to form a trench (opening) 135 in the photo resist film 134 which is shaped so as to correspond to an area in which an interconnect is to be formed (see FIG. 12A).
Then, the photo resist film 134 is used as a mask to etch the polishing stop film 133 and the insulator film 132 to form a trench 136 shaped so as to correspond to an area in which an interconnect is to be formed (see FIG. 12B).
Then, a barrier film for copper diffusion 137 and a copper seed layer 138 are formed on the insulator film 132 and polishing stop film 133, in which the trench 136 has been formed (see FIG. 12C). Reference numeral 139 in FIG. 12C denotes a trench resulting from the formation of the barrier film for copper diffusion 137 and the copper seed layer 138.
Then, one of the above various methods is used to form a copper conductive layer 140 on the copper seed layer 138 (see FIG. 12D).
Then, the CMP process is used to remove the copper conductive layer 140, copper seed layer 138, barrier film for copper diffusion 137 from the polishing stop film 133 until the polishing stop film 133 is exposed. Thus, a buried copper interconnect pattern is formed with the copper conductive layer remaining only inside the trench (see FIG. 12E).
However, the above various conventional methods have the problems described below.
First, the damascene process, which has been actively examined for LSIs, ULSIs, and the like, requires a insulator film forming step, a photo-lithography step, an etching step, and a step of forming a polishing stop film to form a trench in which an interconnect is to be buried, and a via that connects and an upper and lower electrodes together. So, formation process is complicated, and manufacturing cost becomes high.
Further, the thickness of a conductive layer must be increased in order to reduce the interconnect resistance. However, the use of a trench or a via hole with a high aspect ratio prevents copper from being properly buried.
Furthermore, there is disadvantageously a decrease in the throughput of the CMP process or another process for removing unwanted parts after forming a thin copper film all over the substrate.
Moreover, a large-sized CMP apparatus has been developed for a wafer of diameter about 12 inches on which an LSI or a ULSI is produced. However, display devices represented by liquid crystal display devices require a polishing process that can accurately achieve flatness over a larger area than LSIs. Thus, it is difficult to put this apparatus to practical use in applying the apparatus to display devices represented by liquid crystal display devices.
Moreover, in the case of such a large substrate as used in a liquid crystal display device, the area of a thin copper film part used as an interconnect is very small compared to the area of the glass substrate. Thus, even if it is possible to polish all the surface by the CMP or achieve removal by etching, most of the thin copper film formed is removed and discarded. As a result, copper, which is an expensive material, is very inefficiently used. This results in problems such as an increase in product price.